1. Field of Invention
This invention relates to operation of memory devices, and more particularly to a method of programming a cell in a memory (array) that shares an S/D region with another cell, and to a memory apparatus utilizing the method.
2. Description of Related Art
Non-volatile memory devices have been widely used in the fields of long-term storage as being able to retain data without a power and having smaller sizes. For the convenience of use, most of current non-volatile memory devices are programmed and erased electrically. FIGS. 1-3 respectively illustrate three types of non-volatile memory cell and their respective programming methods in the prior art.
Referring to FIG. 1, the memory cell includes a substrate 100, a control gate 110, a floating gate 120, a select gate 130 and S/D regions 140, 150 and 160. To program the cell, the channels under the gates 130 and 120 are turned on by gate voltages Vgs and Vgc, and a source voltage Vs and a higher drain voltage Vd are applied to the S/D regions 140 and 150 respectively to induce an electron current from 140 to 150 through 160 and cause hot electrons under the floating gate 120 to be injected. Such a cell needs a large area so that the integration degree of the memory cells is reduced.
Referring to FIG. 2, the cell includes a substrate 200, a control gate 210, a charge trapping layer 220, and two S/D regions 240 and 250. To program the cell, the channel under the trapping layer 220 is turned on by Vg, and Vs and Vd applied to the regions 240 and 250 respectively to induce an electron current from 240 to 250 and cause hot electrons under the trapping layer 220 to be injected. The cell needs a smaller area, but the unselected cells coupled to the bit lines coupled to the programmed cell easily suffer from a punch-through issue. Though a certain raise in Vs prevents punch-through of unselected cells in the programming, the programming efficiency is reduced thereby.
Referring to FIG. 3, in the non-volatile memory, a cell 302 has a storage layer 320a and an S/D region 350 in the substrate 300 and shares an S/D region 360 with a neighboring cell 304 that has a storage layer 320b and an S/D region 340. The control gates 310 of the cells 302 and 304 are contiguous. The channels under the storage layers 320a and 320b are turned on by Vg, and Vs and Vd are applied to the regions 340 and 350 respectively to induce an electron current from 340 to 350 through 360 and cause hot electrons under the storage layer 320a to be injected. Each cell needs a small area and punch-through of unselected cells is avoided due to the reduced electric field in this case, but the programming efficiency is reduced due to more electron scattering.